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IS61LV12816L IS61LV12816LL
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
* High-speed access time: IS61LV12816L: 8, 10 ns IS61LV12816LL: 12 ns * Operating Current: IS61LV12816L: 50mA (typ.) IS61LV12816LL: 30mA (typ.) * Stand by Current: IS61LV12816L: 700A (typ.) IS61LV12816LL: 400A(typ.) * TTL and CMOS compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available
ISSI
JUNE 2003
(R)
DESCRIPTION
The ISSI IS61LV12816L/IS61LV12816LL is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV12816L/IS61LV12816LL is packaged in the JEDEC standard 44-pin TSOP (Type II), 44-pin LQFP, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128Kx16 MEMORY ARRAY
VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB
CONTROL CIRCUIT
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
1
IS61LV12816L, IS61LV12816LL
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
ISSI
VDD Current ISB1, ISB2 ICC ICC
(R)
Write
ICC
PIN CONFIGURATION 44-Pin TSOP (Type II) (T)
PIN DESCRIPTIONS
A0-A16 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground I/O0-I/O15 CE OE WE LB UB NC VDD GND
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
PIN CONFIGURATION
48-Pin mini BGA (B)
1 2 3 4 5 6
ISSI
44-Pin LQFP (LQ)
A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB
(R)
A B C D E F G H
LB I/O8 I/O9 GND VDD I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
NC I/O0 I/O2 VDD GND I/O6 I/O7 NC
CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7
44 43 42 41 40 39 38 37 36 35 345 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22
WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8
I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
3
IS61LV12816L, IS61LV12816LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VTERM TSTG PT Note: Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.5 to 4.0V -0.5 to VDD + 0.5 -65 to + 150 1.0 Unit V V C W
ISSI
(R)
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature VDD (8 nS) 0C to +70C 3.3V + 10%, -5% -40C to +85C 3.3V + 10%, -5% VDD (10 nS, 12 nS) 3.3V + 10% 3.3V + 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Note:
1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(1) Input Leakage Output Leakage
Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA
Min. 2.4 -- 2 -0.3
Max. -- 0.4 VDD + 0.3 0.8 1 1
Unit V V V V A A
GND VIN VDD GND VOUT VDD, Outputs Disabled
-1 -1
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) IS61LV12816L
Symbol ICC Parameter VDD Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. VDD = Max., VIN = VIH or VIL CE VIH, f = max VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- -- -- -- -- -- 65 70 50 30 35 3 4 700 -10 ns Min. Max. -- -- -- -- -- -- -- -- 60 65 50 25 30 3 4 700
ISSI
Unit mA
(R)
ISB1
mA
ISB2
mA mA A
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% tested.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) IS61LV12816LL
Symbol ICC Parameter VDD Operating Supply Current Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. typ.(2) @ 15ns(3) Com. Ind. Com. Ind. typ.(2) -12 ns Min. Max. -- -- -- -- -- -- -- -- -- 40 45 30 25 20 20 750 900 400 Unit mA
ISB1
TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs)
VDD = Max., VIN = VIH or VIL CE VIH, f = max VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0
mA
ISB2
A A A
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested. 3. For 15ns speed (tAA), Icc is measured at VDD=3.3V, TA=250C. Not 100% tested.
CAPACITANCE(1)
Symbol CIN COUT Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Parameter Input Capacitance Input/Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 6 8
Unit pF pF
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
5
IS61LV12816L, IS61LV12816LL
AC TEST CONDITIONS
Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2
ISSI
(R)
AC TEST LOADS
319 3.3V
ZO = 50 OUTPUT
50 1.5V
OUTPUT
30 pF Including jig and scope
5 pF Including jig and scope
353
Figure 1.
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L -8 ns -10 ns Min. Max Min. Max. 8 -- 3 -- -- -- 0 0 3.5 -- 0 0 -- 8 -- 8 3.5 3.5 -- 3.5 -- 3.5 3.5 -- 10 -- 3 -- -- -- 0 0 3 -- 0 0 -- 10 -- 10 4 4 -- 4 -- 4 4 -- IS61LV12816LL -12 ns Min. Max. 12 -- 3 -- -- -- 0 0 3 -- 0 0 -- 12 -- 12 5 5 -- 5 -- 5 5 --
Symbol
Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE tLZOE
(2) (2)
OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
tHZCE(2) tLZCE(2) tBA tHZB
(2)
tLZB(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
ISSI
(R)
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
LB, UB
DOUT
HIGH-Z
t LZB
t BA
DATA VALID
t HZB
UB_CEDR2.eps
1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
Notes:
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
7
IS61LV12816L, IS61LV12816LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
IS61LV12816L -8 ns -10 ns Min. Max Min. Max. 8 7 7 0 0 6.5 6 6.5 4 0 -- 0 -- -- -- -- -- -- -- -- -- -- 3 -- 10 8 8 0 0 8 7 8 5 0 -- 0 -- -- -- -- -- -- -- -- -- -- 4 -- IS61LV12816LL -12 ns Min. Max. 12 8 8 0 0 9 8 10 6 0 -- 0 -- -- -- -- -- -- -- -- -- -- 5 --
ISSI
Unit ns ns ns ns ns ns ns ns ns ns ns ns
(R)
Symbol
Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End
tWC tSCE tAW tHA tSA tPBW tPWE1 tPWE2 tSD tHD tHZWE tLZWE
Notes:
(3) (3)
WE LOW to High-Z Output WE HIGH to Low-Z Output
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
9
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS OE CE
VALID ADDRESS
LOW
t HA
LOW
t AW t PWE2
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
ADDRESS 1
ISSI
t WC
ADDRESS 2
(R)
OE
t SA
CE
LOW
WE
t HA t SA t PBW t PBW
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
11
IS61LV12816L, IS61LV12816LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE VDD - 0.2V Com. (L) Ind. (L) Com. (LL) Ind. (LL) Options Min. 2.0 -- -- -- -- 0 Typ.(1) -- 0.7 -- 0.4 -- -- --
ISSI
Max. 3.6 3 4 0.75 0.9 -- -- Unit V mA mA ns ns
(R)
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
O
tRC
Note 1: Typical values are measured at VDD = 3.3V, TA = 25 C. Not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR VDD
Data Retention Mode
tRDR
VDR CE VDD - 0.2V
CE GND
12
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
IS61LV12816L, IS61LV12816LL
ORDERING INFORMATION: IS61LV12816L Commercial Range: 0C to +70C
Speed (ns) 8 Order Part No. IS61LV12816L-8B IS61LV12816L-8LQ IS61LV12816L-8T IS61LV12816L-10LQ IS61LV12816L-10T Package mini BGA (6mm x 8mm) LQFP Plastic TSOP (Type II) LQFP Plastic TSOP (Type II)
ISSI
(R)
10
ORDERING INFORMATION: IS61LV12816L Industrial Range: -40C to +85C
Speed (ns) 8 Order Part No. IS61LV12816L-8BI IS61LV12816L-8LQI IS61LV12816L-8TI IS61LV12816L-10BI IS61LV12816L-10LQI IS61LV12816L-10TI Package mini BGA (6mm x 8mm) LQFP Plastic TSOP (Type II) mini BGA (6mm x 8mm) LQFP Plastic TSOP (Type II)
10
ORDERING INFORMATION: IS61LV12816LL Commercial Range: 0C to +70C
Speed (ns) 12 Order Part No. IS61LV12816LL-12T Package Plastic TSOP (Type II)
ORDERING INFORMATION: IS61LV12816LL Industrial Range: -40C to +85C
Speed (ns) 12 Order Part No. IS61LV12816LL-12BI IS61LV12816LL-12LQI IS61LV12816LL-12TI Package mini BGA (6mm x 8mm) LQFP Plastic TSOP (Type II)
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/28/03
13
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (48-pin)
Top View 1 2 3 4 56 6
ISSI
Bottom View
b (48x)
(R)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
A2 SEATING PLANE A1
A
Notes: 1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.24 0.60 7.90 5.90
mBGA - 8mm x 10mm
INCHES Min. Typ. Max. Sym.
N0. Leads
MILLIMETER Min. Typ. Max.
48 -- 0.24 0.60 9.90 7.90 -- -- -- -- -- 1.20 0.30 -- 10.10 8.10 --
INCHES Min. Typ. Max.
Min. Typ. Max.
48 -- -- -- -- -- 1.20 0.30 -- 8.10 6.10
-- 0.009 0.024 0.311 0.232
-- -- -- -- --
0.047 0.012 -- 0.319 0.240
A A1 A2 D D1 E E1 e b
-- -- -- -- --
0.047 0.012 -- 0.398 0.319
0.009 0.024 0.390 0.311
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 01/15/03
PACKAGING INFORMATION
LQFP (Low Profile Quad Flat Pack) Package Code: LQ (44-pin)
D D1
ISSI
(R)
E
E1
b e SEATING PLANE
L1 L
A2 A A1
Low Profile Quad Flat Pack (LQ) Ref. Std. MS-026 No. Leads 44 Millimeters Inches Symbol Min Max Min Max A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.30 0.45 0.012 0.018 C 0.09 0.20 0.004 0.008 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.394 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.394 BSC e 0.80 BSC 0.031 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. 0o 7o 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 include mold mismatch. 3. Controlling dimension: millimeters.
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 05/30/03
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
ISSI
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
N/2+1
E1
E
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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